Provably Trustworthy and Secure Hardware Design with Low Overhead

Due to the globalization of IC design in the semiconductor industry and outsourcing of chip manufacturing, 3PIPs become vulnerable to IP piracy, reverse engineering, counterfeit IC, and hardware Trojans. To thwart such attacks, ICs can be protected using logic encryption techniques. However, strong resilient techniques incur significant overheads. SCAs further complicate matters by introducing potential attacks post-fabrication. One of the most severe SCAs is PA attacks, in which an attacker can observe the power variations of the device and analyze them to extract the secret key. PA attacks can be mitigated via adding large extra hardware; however, the overheads of such solutions can render them impractical, especially when there are power and area constraints. In our first approach, we present two techniques to prevent normal attacks. The first one is based on inserting MUX equal to half/full of the output bit number. In the second technique, we first design PLGs using SiNW FETs and then replace some logic gates in the original design with their SiNW FETs-based PLGs counterparts. In our second approach, we use SiNW FETs to produce obfuscated ICs that are resistant to advanced reverse engineering attacks. Our method is based on designing a small block, whose output is untraceable, namely URSAT. Since URSAT may not offer very strong resilience against the combined AppSAT-removal attack, S-URSAT is achieved using only CMOS-logic gates, and this increases the security level of the design to robustly thwart all existing attacks. In our third topic, we present the usage of ASLD to produce secure and resilient circuits that withstand IC attacks (during the fabrication) and PA attacks (after fabrication). First, we show that ASLD has unique features that can be used to prevent PA and IC attacks. In our three topics, we evaluate each design based on performance overheads and security guarantees

E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion

Due to the outsourcing of chip manufacturing, countermeasures against Integrated Circuit (IC) piracy, reverse engineering, IC overbuilding and hardware Trojans (HTs) become a hot research topic. To protect an IC from these attacks, logic encryption techniques have been considered as a low-cost defense mechanism. In this paper, our proposal is to insert the multiplexer (MUX) with two cases: (i) we randomly insert MUXs equal to half of the output bit number (half MUX insertions); and (ii) we insert MUXs equal to the number of output bits (full MUX insertions). Hamming distance is adopted as a security evaluation. We also measure the delay, power and area overheads with the proposed technique

Logic Obfuscation Against Ic Reverse Engineering Attacks Using Plgs

A strong logic locking approach could be utilized to contest serious threats on ICs. However, recent Boolean satisfiability (SAT) attack successfully decrypts all existing logic locking techniques. Even though different methods have been used to make the attack execution time increase exponentially, those methods are vulnerable to tracked and removed resilient SAT structure based attacks. In this work, we use silicon nanowire FETs to produce an obfuscated IC against reverse engineering attacks and reduce the performance penalty by exchanging some logic gates with different polymorphic gates based SiNW FETs and incorporating a small block of circuitry whose output is untraceable

Leveraging All-Spin Logic To Improve Hardware Security

Due to the globalization of Integrated Circuit (IC) design in the semiconductor industry and the outsourcing of chip manufacturing, third Party Intellectual Properties (3PIPs) become vulnerable to IP piracy, reverse engineering, counterfeit IC, and hardware trojans. A designer has to employ a strong technique to thwart such attacks, e.g. using Strong Logic Locking method [1]. But, such technique cannot be used to protect some circuits since the inserted key-gates rely on the topology of the circuit. Also, it requires higher power, delay, and area overheads compared to other techniques. In this paper, we present the use of spintronic devices to help protect ICs with less performance overhead. We then evaluate the proposed design based on security metric and performance overhead. One of the best spintronic device candidates is the All Spin Logic due to its unique properties: small area, no spin-charge signal conversion, and its compatibility with conventional CMOS technology

Resilient Aes Against Side-Channel Attack Using All-Spin Logic

The new generation of spintronic devices, Hybrid Spintronic-CMOS devices including Magnetic Tunnel Junction (MTJ), have been utilized to overcome Moore’s law limitation as well as preserve higher performance with lower cost. However, implementing these devices as a hardware cryptosystem is vulnerable to side channel attacks (SCAs) due to the differential power at the output of the Hybrid Spintronic-CMOS device and asymmetric read/write operations in MTJ. One of the most severe SCAs is the power analysis attack (PAA), in which an attacker can observe the output current of the device and extract the secret key. In this paper, we employ the All Spin Logic Device (ASLD) to implement protected AES cryptography for the first time. More precisely, we realize that in additional to ASLD features, such as small area, non-volatile memory, high density and low operating voltage, this device has another unique feature: identical power dissipation through the switching operations. Such properties can be effectively leveraged to prevent SCA

Towards Adversarial Attacks for Clinical Document Classification

Regardless of revolutionizing improvements in various domains thanks to recent advancements in the field of Deep Learning (DL), recent studies have demonstrated that DL networks are susceptible to adversarial attacks. Such attacks are crucial in sensitive environments to make critical and life-changing decisions, such as health decision-making. Research efforts on using textual adversaries to attack DL for natural language processing (NLP) have received increasing attention in recent years. Among the available textual adversarial studies, Electronic Health Records (EHR) have gained the least attention. This paper investigates the effectiveness of adversarial attacks on clinical document classification and proposes a defense mechanism to develop a robust convolutional neural network (CNN) model and counteract these attacks. Specifically, we apply various black-box attacks based on concatenation and editing adversaries on unstructured clinical text. Then, we propose a defense technique based on feature selection and filtering to improve the robustness of the models. Experimental results show that a small perturbation to the unstructured text in clinical documents causes a significant drop in performance. Performing the proposed defense mechanism under the same adversarial attacks, on the other hand, avoids such a drop in performance. Therefore, it enhances the robustness of the CNN model for clinical document classification

E\u3csup\u3e2\u3c/sup\u3eLemi:Energy-Efficient Logic Encryption Using Multiplexer Insertion

Due to the outsourcing of chip manufacturing, countermeasures against Integrated Circuit (IC) piracy, reverse engineering, IC overbuilding and hardware Trojans (HTs) become a hot research topic. To protect an IC from these attacks, logic encryption techniques have been considered as a low-cost defense mechanism. In this paper, our proposal is to insert the multiplexer (MUX) with two cases: (i) we randomly insert MUXs equal to half of the output bit number (half MUX insertions); and (ii) we insert MUXs equal to the number of output bits (full MUX insertions). Hamming distance is adopted as a security evaluation. We also measure the delay, power and area overheads with the proposed technique

E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion

Due to the outsourcing of chip manufacturing, countermeasures against Integrated Circuit (IC) piracy, reverse engineering, IC overbuilding and hardware Trojans (HTs) become a hot research topic. To protect an IC from these attacks, logic encryption techniques have been considered as a low-cost defense mechanism. In this paper, our proposal is to insert the multiplexer (MUX) with two cases: (i) we randomly insert MUXs equal to half of the output bit number (half MUX insertions); and (ii) we insert MUXs equal to the number of output bits (full MUX insertions). Hamming distance is adopted as a security evaluation. We also measure the delay, power and area overheads with the proposed technique

Logic Locking Using Hybrid Cmos And Emerging Sinw Fets

The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP) protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs) to replace the conventional Exclusive-OR (XOR)-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead

Ultra‐Low‐Power Design And Hardware Security Using Emerging Technologies For Internet Of Things

In this review article for Internet of Things (IoT) applications, important low‐power design techniques for digital and mixed‐signal analog-digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non‐volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy‐constrained hardware security issues are reviewed. Specifically, light‐weight encryption‐based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all‐spin logic devices are highlighted. Furthermore, a novel ultra‐low power design using bio‐inspired neuromorphic computing and spiking neural network security are discussed